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SEALSQ Launches QASIC Initiative: A Strategic Roadmap for Quantum-Resistant Hardware Security

SEALSQ Corp, a renowned leader in semiconductor, Post-Quantum Cryptography (PQC), and Public Key Infrastructure (PKI) solutions, has announced a significant strategic step to solidify the global digital infrastructure in response to the imminent cryptographic threat posed by future quantum computing. After recently acquiring the French ASIC design firm IC’Alps, the company has formally launched the QASIC (Quantum ASIC) program, making it the cornerstone of its recently integrated strategy.

The ambitious effort is expected to speed the development of secure microcontrollers and quantum-resistant HSMs. These elements protect financial transactions, critical infrastructure, and the rapidly developing IoT environment. Through the integration of IC’Alps’ well-established proficiency in custom integrated circuit design and SEALSQ’s groundbreaking PQC-enabled chip technology, the Quantum ASIC initiative seeks to provide an unparalleled, cohesive, end-to-end security solution that is tailored to the cryptographic challenges of the quantum future.

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The Quantum Wake-Up Call: Why Specialized Hardware is Essential

Future large-scale quantum computers’ theoretical potential are the primary source of the urgency behind the Quantum ASIC program. In particular, methods like Shor’s algorithm can effectively crack the fundamental public-key cryptosystems like Elliptic Curve Cryptography (ECC) and RSA, which now protect the great majority of digital identification, e-commerce, and online communication systems worldwide. “Harvest Now, Decrypt Later” is a crucial idea, even though a cryptographically relevant quantum computer (CRQC) might not be available for several years. This implies that enemies could store sensitive material that has been encrypted today and then decrypt it once such a machine is operating.

A worldwide technological response to this ubiquitous “quantum threat” is Post-Quantum Cryptography (PQC), which has been developed and defined. PQC algorithms are being finalized through the US National Institute of Standards and Technology (NIST) procedure and are based on mathematical problems that are thought to be unsolvable by both classical and quantum computers.

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However, a significant hardware redesign is required for the successful integration of these intricate, novel PQC algorithms into current electronic systems. The computationally demanding nature of PQC implementation necessitates the use of specialized hardware, particularly Application-Specific Integrated Circuits (ASICs), in order to achieve the necessary high speed, low power consumption, and overall efficiency, particularly on embedded and Internet of Things platforms.

Microprocessors or conventional field-programmable gate arrays (FPGAs) frequently cannot manage the higher computational load and larger key sizes that are intrinsic to PQC algorithms. A dedicated, certified, and physically strong layer of security can be provided by custom QASICs, which can be designed from the ground up to run these algorithms with optimal performance and low latency. The Quantum ASIC initiative finds its distinct place in the market right here.

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A Synergistic Integration: SEALSQ and IC’Alps

The strategic merger of IC’Alps’ and SEALSQ’s core skills is the cornerstone of the Quantum ASIC program. Having previously pushed for the incorporation of PQC standards into safe chips, SEALSQ offers acknowledged experience in the fields of certified semiconductor manufacturing, secure silicon design, and Post-Quantum Cryptography intellectual property (IP).

The essential component is provided by IC’Alps, a renowned French design firm with extensive, specialized experience in designing custom analog, mixed-signal, and RISC-V based ASICs. The open-source RISC-V instruction set architecture is the perfect framework for creating the highly specialized secure microcontrollers required for the Quantum ASIC roadmap because it provides unmatched flexibility and customization capability.

With the capacity to manage a secure chip’s whole lifecycle, SEALSQ is able to provide an unparalleled unified solution. Beginning with the initial specification of a secure architecture and the establishment of PQC intellectual property, this end-to-end process includes bespoke physical design, certified production, and continuous lifecycle management.

“The integration of IC’Alps is a major accelerator for their roadmap towards delivering truly quantum-resistant systems,” said Carlos Moreira, CEO of SEALSQ, highlighting the expedited vision brought about by the merger. He added that IC’Alps’ ASIC design skills and their PQC experience combine to provide scalable, tailored security solutions that the market sorely needs. This endeavor is “not just an upgrade; it’s a complete re-engineering of security for the quantum era,” according to Moreira’s conclusion.

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The Three-Phase Quantum ASIC Roadmap

The Quantum ASIC program is organised according to a thorough, three-phase roadmap that aims to both construct the intricate infrastructure needed for the future and offer urgent security solutions:

1. Short-Term (Immediate Commercialization): The company’s first PQC standard chip will be the primary focus of the initial phase. These chips give early adopters easily accessible, certified PQC solutions for instant testing and deployment by leveraging SEALSQ’s current PQC IP and technology stack. During this stage, clients are onboarded and the crucial cryptographic transition process is started.
2. Mid-Term (Custom QASIC Development): This stage is the initiative’s core and is focused on creating custom IC solutions, the core QASIC, and associated security intellectual property. In order to provide customized, high-performance ASICs for particular client demands in vital industries including government, banking, and industrial IoT, SEALSQ will take advantage of IC’Alps’ design experience. To ensure long-term cryptographic agility and greater performance over general-purpose hardware, these QASICs will be deliberately optimized for the final PQC algorithms chosen by NIST.
3. Longer-Term (Next-Generation Secure Systems): This last stage focusses on secure system solutions for next-generation designs, with an eye towards the future of semiconductor architecture. One important example of this is the creation of Chiplet-based Hardware Security Modules (CHSMs). Chiplet technology offers significant advantages in terms of cost, yield, and customization. It entails the production of smaller, modular dies that are then joined on a single package. Through the development of CHSMs, SEALSQ can produce extremely flexible, scalable, and secure computing components that are intended for incorporation into upcoming data centers and computing platforms, guaranteeing that security is ingrained at the most fundamental hardware level.

This methodical, staged strategy ensures that SEALSQ can both drive innovation towards tomorrow’s complex systems and satisfy the market’s present demands for quick PQC solutions.

With preferred partner status with key worldwide semiconductor foundries like TSMC and GlobalFoundries, IC’Alps’ extensive industry contacts enhance the roadmap’s scalability and success. These partnerships ensure access to advanced, high-volume manufacturing nodes. The time-to-market for the new PQC-enabled chips is anticipated to be greatly accelerated by utilising these channels.

The first prototype is anticipated to be delivered in 2026, which is a specific and challenging short-term objective specified by the integrated QASIC roadmap. This significant turning point will verify the combined technology approach and pave the way for commercial deployment. SEALSQ is actively strengthening its global “Quantum Corridor” by establishing itself as a leader in the provision of secure intellectual property and quantum-resistant ASICs. This tactic entails cultivating an international network of clients, partners, and educational institutions committed to the smooth adoption of PQC standards. In order to ensure that the digital world is ready for the impending entrance of the quantum era, the Quantum ASIC program represents a fundamental investment in the resilience of global infrastructure.

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